Apparatus for decoding video data

ABSTRACT

A decoding apparatus decodes symbols and header data obtained by variable length decoding. The decoding apparatus comprises a data distributor (10) for receiving the symbols and alternately outputting blocks of the symbols via two output terminals. A header analyzer (50) receives the header data, analyzes the received header data and outputs parameters relating to restoration of the symbols. DC component decoding unit (40) detects symbols relating to DC coefficients of an intra-macroblock among the symbols output from the data distributor (10), and restores the DC coefficients of the intra-macroblock using the detected symbols and the parameters supplied from the header analyzer (50). First and second restoring units (20 and 30) which are individually connected to two output terminals of said data distributor (10) restore the symbols input from the data distributor (10) in units of a block, using the parameters generated by said header analyzer (50) and a corresponding DC coefficient of the DC coefficients produced by said DC component decoding unit (40).

BACKGROUND OF THE INVENTION

The present invention relates to an apparatus for decoding video data,and more particularly, to an apparatus for decoding video data on areal-time basis by restoring DC coefficients of intra-macroblocks via adecoding path different from those for decoding other coefficients.

DESCRIPTION OF THE RELATED ART

Generally, a decoder relating to an MPEG (Moving Pictures Experts Group)standard receives a bitstream which is coded by an encoder andtransmitted, and restores the received bitstream to the original databefore encoding on the basis of the analysis of header informationcontained in the received bitstream. A general video decoder can decodedata of a main level having a small amount of encoding at the operatingspeed of a system clock. Therefore, header information and encoded datacan be processed via a single path.

However, a video decoder, such as for high-definition TV (HDTV) whichprocesses a bitstream belonging to a main profile and high level in theMPEG standard, requires a system clock of at least 100 MHz in order toperform high-speed data processing since there is a large amount of datato be processed. It is difficult to implement such a system in hardware,and the manufacturing cost of such an implementation is excessivelyhigh.

A technique for reducing the burden of a system clock in a system fordecoding video data in an HDTV is disclosed in Korean Patent ApplicationNo. 95-43583, which is by the applicant of the present invention. Thisprior art discloses a decoding apparatus for decoding via two paths fourluminance blocks and two chrominance blocks which constitute amacroblock relating to a 4:2:0 picture format. This decoding apparatuscan process a video bitstream at a high speed without increasing thespeed of system clock.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an apparatus fordecoding video data in which, among data output from a variable lengthdecoder, data involving DC coefficients of an intra-macroblock isdecoded via a decoding path different from those of other coefficients.Accordingly, the apparatus according to the invention can restore the DCcoefficients on a real-time basis, while reducing its decoding burden.

To accomplish the above object of the present invention, there isprovided a decoding apparatus for decoding symbols and header dataobtained by variable length decoding, the decoding apparatus comprising:

a data distributor for receiving the symbols and alternately outputtingblocks of the symbols via two output terminals;

a header analyzer for receiving the header data, analyzing the receivedheader data and outputting parameters relating to restoration of thesymbols;

DC component decoding means for detecting symbols relating to DCcoefficients of an intra-macroblock among the symbols output from thedata distributor, and restoring the DC coefficients of theintra-macroblock, using the detected symbols and the parameters suppliedfrom the header analyzer; and

first and second restoring units which are individually connected to twooutput terminals of the data distributor, for restoring the symbolsinput from the data distributor in units of a block, using theparameters generated by the header analyzer and a corresponding DCcoefficient of the DC coefficients produced by said DC componentdecoding means.

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiment is described with reference to the drawingswherein:

FIG. 1 is a block diagram of a decoding apparatus according to apreferred embodiment of the present invention;

FIGS. 2A to 2L are timing diagrams for explaining the operation of thedecoding apparatus of FIG. 1;

FIGS. 3A to 3L are timing diagrams for explaining the operation of a DCdecoding unit;

FIG. 4 is a conceptual diagram for explaining reset points in time of DCpredictors within a macroblock; and

FIGS. 5A to 5E are timing diagrams for explaining the latching operationof decoded DC coefficients.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1 illustrating a decoding apparatus of the presentinvention, a data distributor 10 receives symbols and header data outputfrom a variable length decoder (VLD; not shown). The data distributor 10distributes, in units of a block on the basis of the received headerdata, the symbols output from the variable length decoder to a firstrestoring unit 20 and a second restoring unit 30, each of which consistsof a first restoring path and a second restoring path. The datadistributor 10 includes a demultiplexer 11 and first and secondfirst-in-first-out (FIFO) memories 12 and 13, respectively. Thedemultiplexer 11 outputs the received header data to a header analyzer50, and alternatively supplies the symbols to the first FIFO memory 12and the second FIFO memory 13 in block units. The output of the firstFIFO memory 12 is input to the first restoring unit 20, and the outputof the second FIFO memory 13 is input to the second restoring unit 30.The first and second restoring units 20 and 30, respectively, restoredata output from the data distributor 10 using the output data of boththe DC decoding unit 40 and the header analyzer 50. The first restoringunit 20 includes a first run level decoder 21, a first scan converter22, a first inverse quantizer 23 and a first inverse discrete cosinetransformer (IDCT) 24, which are connected in sequence. The secondrestoring unit 30, which receives the output of the second FIFO memory13, includes a second run level decoder 31, a second scan converter 32,a second inverse quantizer 33 and a second inverse discrete cosinetransformer (IDCT) 34, which are connected in sequence.

The DC decoding unit 40 restores DC coefficients of an intra-macroblockfrom the output data of the first and second FIFO memories 12 and 13,respectively, using parameters output from the header decoder 52. Usingthe DC decoding unit 40, the apparatus of FIG. 1 can reduce the burdenof signal processing on the first and second restoring units 20 and 30,respectively. The DC decoding unit 40 receives the outputs of the firstand second FIFO memories 12 and 13, respectively, and of the headeranalyzer 50, and restores the DC coefficients of blocks belonging to theintra-macroblock using the received data. The header analyzer 50includes a header FIFO memory 51 for storing header data output from thedemultiplexer 11, a header decoder 52 and a weighting matrix decoder 53.The header decoder 52 generates parameters involving the restoration ofdata of the first and second restoring units 20 and 30, respectively,using data stored in the header FIFO memory 51. The weighting matrixdecoder 53 generates weighting matrices necessary for inversequantization operations of the first and second inverse quantizers 23and 33, respectively. Each weighting matrix is applied to the first andsecond inverse quantizers 23 and 33, respectively.

The operation of the FIG. 1 apparatus as constructed above will bedescribed in detail involving a 4:2:0 picture format in the MPEG2standard, with reference to FIGS. 2A to 5E.

The macroblock relating to the 4:2:0 picture format is composed of sixblocks, in which one macroblock is encoded in sequence with Y1, Y2, Y3,Y4, Cu and Cv. Here, Y1-Y4 represent luminance blocks and Cu and Cvrepresent chrominance blocks.

The demultiplexer 11 of the data distributor 10 detects header data fromdata received from the variable length decoder (VLD; not shown), andoutputs the detected header data to the header analyzer 50. Thedemultiplexer 11 also identifies the blocks of symbols supplied from thevariable length decoder (not shown) based on the detected header data.The demultiplexer 11 supplies the blocks Y1, Y3 and Cu to the first FIFOmemory 12, and supplies the blocks Y2, Y4 and Cv to the second FIFOmemory 13. The first and second FIFO memories 12 and 13, respectively,output the blocks of symbols in the order in which their are input.

The analysis of header data for a particular macroblock is performed ata point in time preceding by one macroblock, comparing with that for arestoration operation of the symbols of the macroblock. Thus, the firstand second restoring units 20 and 30, respectively, and the DC decodingunit 40 perform an operation with regard to data of the (m-1)-thmacroblock MB(m-1) when the header FIFO memory 51 outputs data of them-th macroblock MB(m). The timing relationship between the data outputof the header FIFO memory 51 and the decoding operation of the first andsecond restoring units 20 and 30, respectively, is 30 shown in FIGS. 2Aand 2B.

The header FIFO memory 51 in the header analyzer 50 stores the headerdata supplied from the demultiplexer 11. The header decoder 52 reads outthe header data stored in the header FIFO memory 51, decodes the readheader data, and generates parameters including a macroblock startsignal MB₋₋ START₋₋ DEC shown in FIG. 2D, a block start signal BLOCK₋₋START shown in FIG. 2E, macroblock position information MB₋₋ COLUMNshown in FIG. 3D, intra-macroblock signal MB₋₋ INTRA shown in FIG. 3Fand a macroblock pattern signal MB₋₋ PATTERN shown in FIG. 3G. Themacroblock start signal MB₋₋ START₋₋ DEC represents a point in time whenrun level decoding and DC decoding begin. The macroblock positioninformation MB₋₋ COLUMN which represents the order of macroblocks, iscalculated using a macroblock escape and a macroblock addressincremented by the variable length decoder. The weighting matrix decoder53 restores data of the weighting matrix by using the header data outputfrom the header FIFO memory 51, and the data of the weighting matrix issupplied to the first and second inverse quantizers 23 and 33,respectively.

The DC decoding unit 40 receives the parameters output from the headerdecoder 51 and the symbols output from the first and second FIFOmemories 12 and 13, respectively. The DC decoding unit 40 detectsmacroblocks using the macroblock start signal MB₋₋ START₋₋ DEC shown inFIG. 3B supplied from the header decoder 52, and generates a macroblockcount signal MB₋₋ COUNT, shown in FIG. 3C, which counts the number ofthe detected macroblocks. When the DC decoding unit 40 receivesmacroblock position information MB₋₋ COLUMN, shown in FIG. 3D, from theheader decoder 52, the DC decoding unit 40 latches the information.Header data and coefficient data with respect to a skipped macroblockare not commonly transmitted. The header decoder 52 reads out from theheader FIFO memory 51 the header data of the (m+3)-th macroblock next toa (m+1)-th macroblock if the (m+2)-th macroblock is a skipped macroblockas shown in FIG. 3A. The DC decoding unit 40 compares the macroblockposition information MB₋₋ COLUMN with the macroblock count signal MB₋₋COUNT. The DC decoding unit 40 resets a skipped detection signal SKIP₋₋DEC to "0" if the two signals MB₋₋ COLUMN and MB₋₋ COUNT do not have thesame value, and again resets the skipped detection signal SKIP₋₋ DEC to"1" if the two signals have the same value. That is, the DC decodingunit 40 causes a value of the skipped detection signal SKIP₋₋ DEC to bereset to "0" when the (m+2)-th macroblock is determined to be theskipped macroblock. As a result, the DC decoding unit 40 generates theskipped detection signal SKIP₋₋ DEC shown in FIG. 3E indicating that theskipped macroblock has been detected.

The DC decoding unit 40 latches the intra-macroblock signal MB₋₋ INTRAand the macroblock pattern signal MB₋₋ PATTERN supplied from the headerdecoder 52. The macroblock pattern signal MB₋₋ PATTERN shown in FIG. 3Ghas a value of "0" when all the symbols of blocks within the macroblockare "0". The DC decoding unit 40 generates an intra-macroblock detectionsignal MB₋₋ INTRA₋₋ DEC shown in FIG. 3H using the two latched signals.The DC decoding unit 40 determines a macroblock to be an"intra-macroblock" when a corresponding intra-macroblock signal MB₋₋INTRA is "1". The DC decoding unit 40 determines a macroblock as an"inter-macroblock" if a corresponding macroblock pattern signal MB₋₋PATTERN is "1" when the intra-macroblock signal MB₋₋ INTRA is "0", anddetermines the macroblock to be an "unnecessary macroblock for codingNOT₋₋ CODED" when both of the two signals are "0". As a result, the DCdecoding unit 40 determines the types of macroblocks, as shown in FIG.3I. Then, the DC decoding unit 40 performs the restoration operationwith respect to DC coefficients of intra-macroblocks. This is becausethe DC coefficients of the intra-macroblock are processed differentlyfrom other coefficients in inverse quantization, and so on. On thecontrary, the DC decoding unit 40 does not perform a decoding operationwith respect to inter-macroblocks, skipped macroblocks and not-codedmacroblocks. Accordingly, the decoding operation of the DC decoding unit40 is in idle status (See FIG. 3J).

The first and second run level decoders 21 and 31, respectively, decodethe symbols output from the FIFO memories 12 and 13, respectively, basedon the parameters supplied by the header analyzer 50. In case of anintra-macroblock, the first and second run level decoders 21 and 31,respectively, perform a run-level-decoding operation based on the blockstart signal BLOCK₋₋ START shown in FIG. 2E supplied by the headerdecoder 52. The first and second scan converters 22 and 32,respectively, perform a scan conversion operation based on the blockstart signal BLOCK₋₋ START shown in FIG. 2E. FIG. 2F shows a timingdiagram relating to the run-level-decoding operation of the first andsecond run level decodes 21 and 31, respectively, and FIG. 2G shows atiming diagram relating to the scan conversion operation of the scanconverters 22 and 32.

The DC decoding unit 40 detects data involving the DC coefficientswithin blocks of the intra-macroblock among the symbols output from thefirst and second FIFO memories 12 and 13, respectively, on the basis ofthe macroblock type signal MB₋₋ TYPE shown in FIG. 2C or 3I. The DCdecoding unit 40 starts to decode the DC coefficients according to theblock start signal BLOCK₋₋ START output from the header decoder 52. TheDC decoding unit 40 restores the DC coefficient of a first path, andthen restores the DC coefficient of a second path after the decoding ofthe DC coefficient via the first path is complete. FIG. 2H shows atiming diagram relating to restoration of the DC coefficient. The DCdecoding unit 40 restores an original DC coefficient by adding a DCcomponent differential value of a DC component size to a DC predictor.In a syntax relating to the MPEG2 standard, the DC component size isrepresented as "DC₋₋ DCT₋₋ SIZE", and the DC component differentialvalue is represented as "DC₋₋ DCT₋₋ DIFFERENTIAL". The first macroblocksignal of a slice SLICE₋₋ ST₋₋ MB shown in FIG. 3K is set when a slicestart signal SLICE₋₋ START₋₋ CODE is detected from the header data, andis reset when the next macroblock start signal MB₋₋ START₋₋ DEC isdetected. Accordingly, "A" in FIG. 3L becomes a point in time to set areset value of the DC predictor. Here, the reset value of the DCpredictor is determined by DC coefficient precision INTRA₋₋ DC₋₋PRECISION included in the picture coding extension PICTURE₋₋ CODING₋₋EXTENSION. If the previous macroblock of a current macroblock is not anintra-macroblock, or the current macroblock is the first macroblock of aslice, the DC predictor of the luminance signal block Y1 is set to afirst reset value, as shown in FIG. 4, and the DC predictors of thechrominance signal blocks Cu and Cv are reset to second and thirdvalues, respectively. The DC predictors of the luminance signal blocksY2, Y3 and Y4 are set to the first reset value of the luminance signalblock Y1. FIG. 2I shows a timing diagram of the DC coefficients of theintra-macroblock generated by the DC decoding unit 40.

The first and second inverse quantizers 23 and 33, respectively,inverse-quantize the data output by the first and second scan converters22 and 32, respectively, using the data of the weighting matrixgenerated by the weighting matrix decoder 53. The output of the firstinverse quantizer 23 is supplied to the first inverse DCT 24, and thatof the second inverse quantizer 33 is supplied to the second inverse DCT34. Referring to FIGS. 5A to 5E showing timing diagrams relating to theinverse DCTs 24 and 34, the first and second inverse DCTs 24 and 34,respectively, generate a macroblock start latching signal MB₋₋ START₋₋LCH as shown in FIG. 5D, based on the macroblock start signal MB₋₋START₋₋ DEC generated by the header decoder 52, and produces anintra-macroblock latching signal MB₋₋ INTRA₋₋ LCH as shown in FIG. 5E,based on the intra-macroblock start signal MB₋₋ INTRA₋₋ DEC. As shown inFIGS. 5C and 5D, the macroblock start latching signal MB₋₋ START₋₋ LCHis a one-block-period-delayed signal as compared with the macroblockstart signal MB₋₋ START₋₋ DEC. The intra-macroblock latching signal MB₋₋INTRA₋₋ LCH is a one-block-period-delayed signal rather than theintra-macroblock start signal MB₋₋ INTRA₋₋ DEC. Accordingly, the inverseDCTs 24 an 34, respectively, generate a block start latching signalBLOCK₋₋ START₋₋ LCH in order to latch the DC coefficients output fromthe DC decoding unit 40. At this time, the block start latching signalBLOCK₋₋ START₋₋ LCH is a signal in which decoding delay in the inversequantizers 23 and 33 is considered. Thus, a timing relationship betweenblocks to be decoded by the inverse DCTs 24 and 34, respectively, andoutputs of the inverse quantizers 23 and 33, respectively, is shownFIGS. 2K and 2L.

The FIG. 1 apparatus describes one embodiment for decoding header dataand symbols in block units, but can be embodied in parallel processcoded coefficients in a row unit of a block.

As described above, the dc decoding unit for a high-speed MPEG decodingapparatus according to the present invention can restore DC coefficientson a real-time basis by decoding DC coefficients of an intra-macroblockvia a separate path with regard to other coefficients.

I claim:
 1. A decoding apparatus for decoding symbols and header dataobtained by variable length decoding, said decoding apparatuscomprising:a data distributor for receiving the symbols and alternatelyoutputting blocks of the symbols via two output terminals; a headeranalyzer for receiving the header data, analyzing the received headerdata and outputting parameters relating to restoration of the symbols; aDC component decoder for detecting symbols relating to DC coefficientsof an intra-macroblock among the symbols output from said datadistributor, and restoring the DC coefficients of the intra-macroblock,using the detected symbols and the parameters supplied from said headeranalyzer; and first and second restoring units, individually connectedto the two output terminals of said data distributor, for restoring theblocks of the symbols output by said data distributor, using theparameters generated by said header analyzer and a corresponding DCcoefficient of the DC coefficients produced by said DC componentdecoder.
 2. The decoding apparatus according to claim 1, wherein saidheader analyzer comprises a FIFO memory for storing the header dataoutput from said data distributor;a header decoder for decoding theheader data stored in said FIFO memory and generating parameters; and aweighting matrix decoder for restoring information of a weighting matrixfor inverse quantization with the header data stored in said FIFOmemory.
 3. The decoding apparatus according to claim 1, wherein said DCcomponent decoder restores a DC coefficient corresponding to each ofblocks constituting an intra-macroblock.
 4. The decoding apparatusaccording to claim 1, wherein said DC component decoder judges whether amacroblock composed of the received symbols is an intra-macroblock,using the parameters output from said header analyzer and the symbolsoutput from said data distributor, restores the DC coefficientsindividually corresponding to blocks composed of the symbols containedin the intra-macroblock, and supplies the restored data to said firstand second restoring units.
 5. The decoding apparatus according to claim1, wherein each of said first and second restoring units comprises aninverse discrete cosine transformer using the DC coefficients restoredby said DC component decoder as the DC coefficient values ofcorresponding blocks within the intra-macroblock.